1. Field of the Invention
The present invention generally relates to a technique for preventing electrostatic discharge damage to integrated circuits. More particularly, the present invention relates to an electrostatic discharge protection circuit that is immune to latch-up during normal operation.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during handling of semiconductor integrated circuit ("IC") devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially, or sometimes completely hamper its operation.
There are several ESD stress models based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standards models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been proposed. The human-body model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. The military standard models the electrostatic stress produced on an IC device when a human carrying electrostatic charges touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electric charges contacts the lead pins of the IC device. The charged device model describes the ESD current generated when an IC already carrying electric charges is grounded while being handled.
However, in light of the trend toward submicron scale IC fabrication, CMOS IC have become more vulnerable to ESD damage due to advanced processes, such as use of a lightly-doped drain ("LDD") structure and clad silicide diffusions. Therefore, lateral silicon-controlled rectifiers (LSCRs) have been utilized as the main components of ESD protection circuits, for facilitating ESD protection. An example, R. N. Rountree et al., "A PROCESS-TOLERANT INPUT PROTECTION CIRCUIT FOR ADVANCED CMOS PROCESSES," has been proposed in EOS/ESD Symp. Proc., EOS-10, pp.201-205, 1988.
Referring to FIG. 1, a conventional lateral silicon-controlled rectifier fabricated onto a semiconductor substrate is schematically depicted in a cross-sectional view. The silicon-controlled rectifier is arranged at an IC pad 1, which is connected to an internal circuit 2 of the integrated circuit device. When ESD stress occurs at the IC pad 1, latch-up of the silicon-controlled rectifier is triggered to conduct the resulting ESD current and, therefore, bypass the ESD stress. This protects the internal circuit 2 from ESD damage.
As shown in FIG. 1, the silicon-controlled rectifier is fabricated on a P-type silicon substrate 3 in which an N-well region 4 is formed. A P-type well region 5, which might optionally be formed in the P-type silicon substrate 3 adjacent to the N-well region 4, is drawn with dashed lines. A first P-type doped region 6 formed in the N-well region 3 is connected to the IC pad 1. A first N-type doped region 7 formed in the P-type silicon substrate 3 (or P-well region 5) is spaced from the N-well region 4 and connected to a circuit grounding node V.sub.SS. Accordingly, the first P-type doped region 6, the N-well region 4, and the P-type silicon substrate 3 (or the P-well region 5), and the first N-type doped region 7 constitute the lateral silicon-controlled rectifier.
In addition, a second N-type doped region 8 is formed in the N-well region 4 as the contact region thereof, and is electrically connected to the first P-type doped region 6 so as to constitute the anode 10 of the silicon-controlled rectifier. A second P-type doped region 9 is 5) formed in the P-type silicon substrate 3 (or P-well region as the contact region thereof, and is electrically connected with the first N-type doped region 7 to constitute the cathode 11 of the silicon-controlled rectifier.
Referring to FIG. 2, the equivalent circuit diagram of the protection circuit shown in FIG. 1 is schematically depicted. In accordance with FIG. 1, the first P-type doped region 6, the N-well region 4, and the P-type silicon substrate 3 (the P-well region 5) serve as the emitter, base, collector, respectively, of a PNP bipolar junction transistor Q.sub.1 depicted in FIG. 2. The N-well region 4, the P-type silicon substrate 3 (or P-well region 5), and the first N-type doped region 7 serve as the collector, base, emitter, respectively, of an NPN bipolar junction transistor Q.sub.2 as depicted in FIG. 2. The base of the transistor Q.sub.2 is tied to the collector of the transistor Q.sub.2, and the collector of the transistor Q.sub.1 is tied to the base of the transistor Q.sub.2, thereby forming the lateral silicon-controlled rectifier. The emitters of the transistors Q.sub.1 and Q.sub.2 are connected to the IC pad 1 and the circuit grounding node V.sub.SS, respectively. Moreover, As shown in FIG. 2, two resistors Rn and Rp represent the spreading resistance of the N-well region 4 and the P-type silicon substrate 3 (or P-well region 5), respectively. For simplicity, a block 20 is used to designate the lateral silicon-controlled rectifier depicted in FIG. 2.
When ESD stress occurs at the IC pad 1, latch-up of the silicon-controlled rectifier is triggered to conduct the resulting ESD current and, therefore, bypass the ESD. This protects the internal circuit 2 from ESD damage.
However, during normal operation, latch-up may be abnormally induced and result in disorder or even error if noise interferes with the integrated circuit.